Messages in this thread | | | From | Dmitry Osipenko <> | Subject | [PATCH v3 0/6] Couple improvements for Tegra clk driver | Date | Tue, 2 Mar 2021 14:51:11 +0300 |
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This series fixes couple minor standalone problems of the Tegra clk driver.
Changelog:
v3: - Added acks from Thierry Reding that he gave to v2.
- Added new patch "clk: tegra: Don't allow zero clock rate for PLLs".
v2: - Added these new patches:
clk: tegra: Halve SCLK rate on Tegra20 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry
v1: - Collected clk patches into a single series.
Dmitry Osipenko (6): clk: tegra30: Use 300MHz for video decoder by default clk: tegra: Fix refcounting of gate clocks clk: tegra: Ensure that PLLU configuration is applied properly clk: tegra: Halve SCLK rate on Tegra20 MAINTAINERS: Hand Tegra clk driver to Jon and Thierry clk: tegra: Don't allow zero clock rate for PLLs
CREDITS | 6 +++ MAINTAINERS | 4 +- drivers/clk/tegra/clk-periph-gate.c | 72 +++++++++++++++++++---------- drivers/clk/tegra/clk-periph.c | 11 +++++ drivers/clk/tegra/clk-pll.c | 12 +++-- drivers/clk/tegra/clk-tegra20.c | 6 +-- drivers/clk/tegra/clk-tegra30.c | 2 +- 7 files changed, 77 insertions(+), 36 deletions(-)
-- 2.29.2
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