Messages in this thread | | | From | Ben Chuang <> | Subject | Re: [PATCH 2/2] mmc: sdhci-pci-gli: GL9755: Issue 8/16-bit MMIO reads as 32-bit reads. | Date | Thu, 9 Dec 2021 20:19:49 +0800 |
| |
Hi Hector,
On Tue, 7 Dec 2021 15:40:19 +0900, Hector Martin <marcan@marcan.st> wrote: > > For some reason, <32-bit reads do not work on Apple ARM64 platforms with > these chips (even though they do on other PCIe devices). Issue them as > 32-bit reads instead. This is done unconditionally, as it shouldn't hurt > even if not necessary. > > Signed-off-by: Hector Martin <marcan@marcan.st> > --- > drivers/mmc/host/sdhci-pci-gli.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > index ad742743a494..31547fed0952 100644 > --- a/drivers/mmc/host/sdhci-pci-gli.c > +++ b/drivers/mmc/host/sdhci-pci-gli.c > @@ -906,7 +906,26 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) > return 0; > } > > +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) > + > +static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) > +{ > + u32 val = readl(host->ioaddr + (reg & ~3)); > + u16 word; > + word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
checkpatch says " WARNING: Missing a blank line after declarations #71: FILE: drivers/mmc/host/sdhci-pci-gli.c:915: + u16 word; + word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; "
> + return word; > +} > + > +static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) > +{ > + u32 val = readl(host->ioaddr + (reg & ~3)); > + u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; > + return byte; > +} > + > static const struct sdhci_ops sdhci_gl9755_ops = { > + .read_w = sdhci_gli_readw, > + .read_b = sdhci_gli_readb,
I think GL9750 also need this patch. Can you help to add these two functions to sdhci_gl9750_ops?
Best regards, Ben
> .set_clock = sdhci_gl9755_set_clock, > .enable_dma = sdhci_pci_enable_dma, > .set_bus_width = sdhci_set_bus_width, > -- > 2.33.0
| |