Messages in this thread | | | From | "Chanho Park" <> | Subject | RE: [PATCH 5/6] i2c: exynos5: Add bus clock support | Date | Thu, 2 Dec 2021 19:30:11 +0900 |
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> In new Exynos SoCs (like Exynos850) where HSI2C is implemented as a part > of USIv2 block, there are two clocks provided to HSI2C controller: > - PCLK: bus clock (APB), provides access to register interface > - IPCLK: operating IP-core clock; SCL is derived from this one > > Both clocks have to be asserted for HSI2C to be functional in that case. > > Add code to obtain and enable/disable PCLK in addition to already handled > operating clock. Make it optional though, as older Exynos SoC variants > only have one HSI2C clock. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Best Regards, Chanho Park
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