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Subject[lunn:v5.15-rc2-net-next-phy-lock 14/14] drivers/net/dsa/b53/b53_common.c:1297:26: error: implicit declaration of function 'b53_adjust_init'; did you mean 'b53_adjust_link'?
tree:   https://github.com/lunn/linux.git v5.15-rc2-net-next-phy-lock
head: a5fc611ff3720771a7c6c8f5acefff8708757020
commit: a5fc611ff3720771a7c6c8f5acefff8708757020 [14/14] net: phy: phy_init_eee: Add locking
config: openrisc-buildonly-randconfig-r002-20210929 (attached as .config)
compiler: or1k-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/lunn/linux/commit/a5fc611ff3720771a7c6c8f5acefff8708757020
git remote add lunn https://github.com/lunn/linux.git
git fetch --no-tags lunn v5.15-rc2-net-next-phy-lock
git checkout a5fc611ff3720771a7c6c8f5acefff8708757020
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=openrisc

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

drivers/net/dsa/b53/b53_common.c: In function 'b53_adjust_link':
>> drivers/net/dsa/b53/b53_common.c:1297:26: error: implicit declaration of function 'b53_adjust_init'; did you mean 'b53_adjust_link'? [-Werror=implicit-function-declaration]
1297 | p->eee_enabled = b53_adjust_init(ds, port, phydev);
| ^~~~~~~~~~~~~~~
| b53_adjust_link
cc1: all warnings being treated as errors


vim +1297 drivers/net/dsa/b53/b53_common.c

1211
1212 static void b53_adjust_link(struct dsa_switch *ds, int port,
1213 struct phy_device *phydev)
1214 {
1215 struct b53_device *dev = ds->priv;
1216 struct ethtool_eee *p = &dev->ports[port].eee;
1217 u8 rgmii_ctrl = 0, reg = 0, off;
1218 bool tx_pause = false;
1219 bool rx_pause = false;
1220
1221 if (!phy_is_pseudo_fixed_link(phydev))
1222 return;
1223
1224 /* Enable flow control on BCM5301x's CPU port */
1225 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1226 tx_pause = rx_pause = true;
1227
1228 if (phydev->pause) {
1229 if (phydev->asym_pause)
1230 tx_pause = true;
1231 rx_pause = true;
1232 }
1233
1234 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1235 tx_pause, rx_pause);
1236 b53_force_link(dev, port, phydev->link);
1237
1238 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1239 if (port == dev->imp_port)
1240 off = B53_RGMII_CTRL_IMP;
1241 else
1242 off = B53_RGMII_CTRL_P(port);
1243
1244 /* Configure the port RGMII clock delay by DLL disabled and
1245 * tx_clk aligned timing (restoring to reset defaults)
1246 */
1247 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1248 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1249 RGMII_CTRL_TIMING_SEL);
1250
1251 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1252 * sure that we enable the port TX clock internal delay to
1253 * account for this internal delay that is inserted, otherwise
1254 * the switch won't be able to receive correctly.
1255 *
1256 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1257 * any delay neither on transmission nor reception, so the
1258 * BCM53125 must also be configured accordingly to account for
1259 * the lack of delay and introduce
1260 *
1261 * The BCM53125 switch has its RX clock and TX clock control
1262 * swapped, hence the reason why we modify the TX clock path in
1263 * the "RGMII" case
1264 */
1265 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1266 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1267 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1268 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1269 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1270 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1271
1272 dev_info(ds->dev, "Configured port %d for %s\n", port,
1273 phy_modes(phydev->interface));
1274 }
1275
1276 /* configure MII port if necessary */
1277 if (is5325(dev)) {
1278 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1279 &reg);
1280
1281 /* reverse mii needs to be enabled */
1282 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1283 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1284 reg | PORT_OVERRIDE_RV_MII_25);
1285 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1286 &reg);
1287
1288 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1289 dev_err(ds->dev,
1290 "Failed to enable reverse MII mode\n");
1291 return;
1292 }
1293 }
1294 }
1295
1296 /* Re-negotiate EEE if it was enabled already */
> 1297 p->eee_enabled = b53_adjust_init(ds, port, phydev);
1298 }
1299

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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