Messages in this thread | | | From | Bhaskara Budiredla <> | Subject | RE: [PATCH v5 3/4] perf/marvell: cn10k DDR perfmon event overflow handling | Date | Mon, 18 Oct 2021 04:37:49 +0000 |
| |
>Two fixed event counters starts counting from zero on overflow, so overflow >condition is when new count less than previous count. While eight >programmable event counters freezes at maximum value. Also individual >counter cannot be restarted, so need to restart all eight counters. > >Signed-off-by: Bharat Bhushan <bbhushan2@marvell.com> >---
Reviewed-by: Bhaskara Budiredla <bbudiredla@marvell.com>
| |