Messages in this thread | | | Subject | Re: [PATCH v5 14/15] clk: at91: sama7g5: set low limit for mck0 at 32KHz | From | Nicolas Ferre <> | Date | Fri, 15 Oct 2021 10:07:29 +0200 |
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On 11/10/2021 at 13:27, Claudiu Beznea wrote: > MCK0 could go as low as 32KHz. Set this limit. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> --- > drivers/clk/at91/sama7g5.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c > index fd9d17eabf54..369dfafabbca 100644 > --- a/drivers/clk/at91/sama7g5.c > +++ b/drivers/clk/at91/sama7g5.c > @@ -850,7 +850,7 @@ static const struct { > > /* MCK0 characteristics. */ > static const struct clk_master_characteristics mck0_characteristics = { > - .output = { .min = 50000000, .max = 200000000 }, > + .output = { .min = 32768, .max = 200000000 }, > .divisors = { 1, 2, 4, 3, 5 }, > .have_div3_pres = 1, > }; >
-- Nicolas Ferre
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