Messages in this thread | | | Subject | Re: [PATCH v5 08/15] clk: at91: clk-master: check if div or pres is zero | From | Nicolas Ferre <> | Date | Fri, 15 Oct 2021 09:55:35 +0200 |
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On 11/10/2021 at 13:27, Claudiu Beznea wrote: > Check if div or pres is zero before using it as argument for ffs(). > In case div is zero ffs() will return 0 and thus substracting from > zero will lead to invalid values to be setup in registers. > > Fixes: 7a110b9107ed8 ("clk: at91: clk-master: re-factor master clock") > Fixes: 75c88143f3b87 ("clk: at91: clk-master: add master clock support for SAMA7G5") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> --- > drivers/clk/at91/clk-master.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c > index 9a2c8e64cacf..2093e13b5068 100644 > --- a/drivers/clk/at91/clk-master.c > +++ b/drivers/clk/at91/clk-master.c > @@ -344,7 +344,7 @@ static int clk_master_pres_set_rate(struct clk_hw *hw, unsigned long rate, > > else if (pres == 3) > pres = MASTER_PRES_MAX; > - else > + else if (pres) > pres = ffs(pres) - 1; > > spin_lock_irqsave(master->lock, flags); > @@ -757,7 +757,7 @@ static int clk_sama7g5_master_set_rate(struct clk_hw *hw, unsigned long rate, > > if (div == 3) > div = MASTER_PRES_MAX; > - else > + else if (div) > div = ffs(div) - 1; > > spin_lock_irqsave(master->lock, flags); >
-- Nicolas Ferre
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