Messages in this thread | | | From | wefu@redhat ... | Subject | [PATCH 0/2] riscv: Add RISC-V svpbmt extension supports | Date | Wed, 13 Oct 2021 02:33:42 +0800 |
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From: Fu Wei <fu.wei@linaro.org>
This patch follows the standard pure RISC-V Svpbmt extension in privilege spec to solve the non-coherent SOC DMA synchronization issues.
Wei Fu (2): dt-bindings: riscv: Add mmu-supports with svpbmt riscv: Add RISC-V svpbmt supports
.../devicetree/bindings/riscv/cpus.yaml | 5 +++ arch/riscv/include/asm/fixmap.h | 2 +- arch/riscv/include/asm/pgtable-64.h | 8 ++-- arch/riscv/include/asm/pgtable-bits.h | 41 ++++++++++++++++++- arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++---- arch/riscv/kernel/cpufeature.c | 32 +++++++++++++++ arch/riscv/mm/init.c | 5 +++ 7 files changed, 117 insertions(+), 15 deletions(-)
-- 2.25.4
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