Messages in this thread Patch in this message | | | From | Alexander A Sverdlin <> | Subject | [PATCH 4/6] MIPS: Octeon: qspinlock: Exclude mmiowb() | Date | Wed, 27 Jan 2021 21:36:25 +0100 |
| |
From: Alexander Sverdlin <alexander.sverdlin@nokia.com>
On Octeon mmiowb() is SYNCW, which is already contained in smp_store_release(). Removing superfluous barrier brings around 10% performance on uncontended tight spinlock loops.
Signed-off-by: Alexander Sverdlin <alexander.sverdlin@nokia.com> --- arch/mips/include/asm/spinlock.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 0a707f3..fbe97b4 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -21,8 +21,10 @@ */ static inline void queued_spin_unlock(struct qspinlock *lock) { +#ifndef CONFIG_CPU_CAVIUM_OCTEON /* This could be optimised with ARCH_HAS_MMIOWB */ mmiowb(); +#endif smp_store_release(&lock->locked, 0); #ifdef CONFIG_CPU_CAVIUM_OCTEON nudge_writes(); -- 2.10.2
| |