Messages in this thread | | | Date | Fri, 22 Jan 2021 11:58:19 +0000 | From | Catalin Marinas <> | Subject | Re: [PATCH v5 4/6] arm64: mte: Enable async tag check fault |
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On Thu, Jan 21, 2021 at 04:39:41PM +0000, Vincenzo Frascino wrote: > MTE provides a mode that asynchronously updates the TFSR_EL1 register > when a tag check exception is detected. > > To take advantage of this mode the kernel has to verify the status of > the register at: > 1. Context switching > 2. Return to user/EL0 (Not required in entry from EL0 since the kernel > did not run) > 3. Kernel entry from EL1 > 4. Kernel exit to EL1 > > If the register is non-zero a trace is reported. > > Add the required features for EL1 detection and reporting. > > Note: ITFSB bit is set in the SCTLR_EL1 register hence it guaranties that > the indirect writes to TFSR_EL1 are synchronized at exception entry to > EL1. On the context switch path the synchronization is guarantied by the > dsb() in __switch_to(). > The dsb(nsh) in mte_check_tfsr_exit() is provisional pending > confirmation by the architects. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
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