Messages in this thread Patch in this message | | | From | Shunsuke Nakamura <> | Subject | [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA events | Date | Thu, 21 Jan 2021 19:54:23 +0900 |
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Adds L1 data cache refill prefetch, L2 data cache refill prefetch, and DCZVA instruction events.
Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com> --- .../perf/pmu-events/arch/arm64/armv8-recommended.json | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json index d0a1986..ee0e67d 100644 --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json @@ -54,6 +54,12 @@ "BriefDescription": "L1D cache invalidate" }, { + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x49", + "EventName": "L1D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 1 data TLB refill, read", "EventCode": "0x4C", "EventName": "L1D_TLB_REFILL_RD", @@ -120,6 +126,12 @@ "BriefDescription": "L2D cache invalidate" }, { + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.", + "EventCode": "0x59", + "EventName": "L2D_CACHE_REFILL_PRF", + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch." + }, + { "PublicDescription": "Attributable Level 2 data or unified TLB refill, read", "EventCode": "0x5c", "EventName": "L2D_TLB_REFILL_RD", @@ -408,6 +420,12 @@ "BriefDescription": "Release consistency operation speculatively executed, Store-Release" }, { + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.", + "EventCode": "0x9f", + "EventName": "DCZVA_SPEC", + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction." + }, + { "PublicDescription": "Attributable Level 3 data or unified cache access, read", "EventCode": "0xa0", "EventName": "L3D_CACHE_RD", -- 1.8.3.1
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