lkml.org 
[lkml]   [2021]   [Jan]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH v2 1/3] perf vendor events: Add cache refill and DCZVA events
Date
On 21/01/2021 11:39, Shaokun Zhang wrote:
> Hi,
>
> 在 2021/1/21 18:54, Shunsuke Nakamura 写道:
>> Adds L1 data cache refill prefetch, L2 data cache refill prefetch,
>> and DCZVA instruction events.
>
> A silly question, Does Arm define these events? I checked Arm ARM
> document(DDI0487Fc) that these event numbers are reserved. Or maybe
> I miss something.

For events which are reserved (see k3-1), like 0x9f, prob should not be
putting in this file, but rather the CPU JSON.

Cheers,
John

>
>>
>> Signed-off-by: Shunsuke Nakamura <nakamura.shun@jp.fujitsu.com>
>> ---
>> .../perf/pmu-events/arch/arm64/armv8-recommended.json | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> index d0a1986..ee0e67d 100644
>> --- a/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> +++ b/tools/perf/pmu-events/arch/arm64/armv8-recommended.json
>> @@ -54,6 +54,12 @@
>> "BriefDescription": "L1D cache invalidate"
>> },
>> {
>> + "PublicDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch.",
>> + "EventCode": "0x49",
>> + "EventName": "L1D_CACHE_REFILL_PRF",
>> + "BriefDescription": "This event counts L1D_CACHE_REFILL caused by software or hardware prefetch."
>> + },
>> + {
>> "PublicDescription": "Attributable Level 1 data TLB refill, read",
>> "EventCode": "0x4C",
>> "EventName": "L1D_TLB_REFILL_RD",
>> @@ -120,6 +126,12 @@
>> "BriefDescription": "L2D cache invalidate"
>> },
>> {
>> + "PublicDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch.",
>> + "EventCode": "0x59",
>> + "EventName": "L2D_CACHE_REFILL_PRF",
>> + "BriefDescription": "This event counts L2D_CACHE_REFILL caused by software or hardware prefetch."
>> + },
>> + {
>> "PublicDescription": "Attributable Level 2 data or unified TLB refill, read",
>> "EventCode": "0x5c",
>> "EventName": "L2D_TLB_REFILL_RD",
>> @@ -408,6 +420,12 @@
>> "BriefDescription": "Release consistency operation speculatively executed, Store-Release"
>> },
>> {
>> + "PublicDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction.",
>> + "EventCode": "0x9f",
>> + "EventName": "DCZVA_SPEC",
>> + "BriefDescription": "This event counts architecturally executed zero blocking operations due to the 'DC ZVA' instruction."
>> + },
>> + {
>> "PublicDescription": "Attributable Level 3 data or unified cache access, read",
>> "EventCode": "0xa0",
>> "EventName": "L3D_CACHE_RD",
>>
> .
>

\
 
 \ /
  Last update: 2021-01-21 18:48    [W:0.109 / U:0.184 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site