Messages in this thread | | | From | Atish Patra <> | Date | Thu, 14 Jan 2021 10:33:01 -0800 | Subject | Re: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32 |
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On Wed, Jan 13, 2021 at 9:10 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote: > > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of > > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock > > allocation if it is requested to be aligned with SMP_CACHE_BYTES. > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > arch/riscv/include/asm/cache.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h > > index 9b58b104559e..c9c669ea2fe6 100644 > > --- a/arch/riscv/include/asm/cache.h > > +++ b/arch/riscv/include/asm/cache.h > > @@ -7,7 +7,11 @@ > > #ifndef _ASM_RISCV_CACHE_H > > #define _ASM_RISCV_CACHE_H > > > > +#ifdef CONFIG_64BIT > > #define L1_CACHE_SHIFT 6 > > +#else > > +#define L1_CACHE_SHIFT 5 > > +#endif > > > > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) > > Should we not instead just > > #define SMP_CACHE_BYTES L1_CACHE_BYTES > > like a handful of architectures do? >
The generic code already defines it that way in include/linux/cache.h
> The cache size is sort of fake here, as we don't have any non-coherent > mechanisms, but IIRC we wrote somewhere that it's recommended to have 64-byte > cache lines in RISC-V implementations as software may assume that for > performance reasons. Not really a strong reason, but I'd prefer to just make > these match. >
If it is documented somewhere in the kernel, we should update that. I think SMP_CACHE_BYTES being 64 actually degrades the performance as there will be a fragmented memory blocks with 32 bit bytes gap wherever SMP_CACHE_BYTES is used as an alignment requirement.
In addition to that, Geert Uytterhoeven mentioned some panic on vex32 without this patch. I didn't see anything in Qemu though.
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-- Regards, Atish
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