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    SubjectRe: [PATCH 3/4] RISC-V: Fix L1_CACHE_BYTES for RV32
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    On Thu, 07 Jan 2021 01:26:51 PST (-0800), Atish Patra wrote:
    > SMP_CACHE_BYTES/L1_CACHE_BYTES should be defined as 32 instead of
    > 64 for RV32. Otherwise, there will be hole of 32 bytes with each memblock
    > allocation if it is requested to be aligned with SMP_CACHE_BYTES.
    >
    > Signed-off-by: Atish Patra <atish.patra@wdc.com>
    > ---
    > arch/riscv/include/asm/cache.h | 4 ++++
    > 1 file changed, 4 insertions(+)
    >
    > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
    > index 9b58b104559e..c9c669ea2fe6 100644
    > --- a/arch/riscv/include/asm/cache.h
    > +++ b/arch/riscv/include/asm/cache.h
    > @@ -7,7 +7,11 @@
    > #ifndef _ASM_RISCV_CACHE_H
    > #define _ASM_RISCV_CACHE_H
    >
    > +#ifdef CONFIG_64BIT
    > #define L1_CACHE_SHIFT 6
    > +#else
    > +#define L1_CACHE_SHIFT 5
    > +#endif
    >
    > #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)

    Should we not instead just

    #define SMP_CACHE_BYTES L1_CACHE_BYTES

    like a handful of architectures do?

    The cache size is sort of fake here, as we don't have any non-coherent
    mechanisms, but IIRC we wrote somewhere that it's recommended to have 64-byte
    cache lines in RISC-V implementations as software may assume that for
    performance reasons. Not really a strong reason, but I'd prefer to just make
    these match.

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