Messages in this thread Patch in this message | | | Date | Wed, 19 Aug 2020 08:52:06 -0000 | From | "tip-bot2 for Kan Liang" <> | Subject | [tip: perf/core] perf/x86: Add a macro for RDPMC offset of fixed counters |
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The following commit has been merged into the perf/core branch of tip:
Commit-ID: 0e2e45e2ded4988f5641115fd996c75dc32e4be3 Gitweb: https://git.kernel.org/tip/0e2e45e2ded4988f5641115fd996c75dc32e4be3 Author: Kan Liang <kan.liang@linux.intel.com> AuthorDate: Thu, 23 Jul 2020 10:11:12 -07:00 Committer: Peter Zijlstra <peterz@infradead.org> CommitterDate: Tue, 18 Aug 2020 16:34:36 +02:00
perf/x86: Add a macro for RDPMC offset of fixed counters
The RDPMC base offset of fixed counters is hard-code. Use a meaningful name to replace the magic number to improve the readability of the code.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200723171117.9918-10-kan.liang@linux.intel.com --- arch/x86/events/core.c | 3 ++- arch/x86/include/asm/perf_event.h | 3 +++ 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 53fcf0a..ebf723f 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1151,7 +1151,8 @@ static inline void x86_assign_hw_event(struct perf_event *event, hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (idx - INTEL_PMC_IDX_FIXED); - hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | 1<<30; + hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | + INTEL_PMC_FIXED_RDPMC_BASE; break; default: diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 000cab7..964ba31 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -196,6 +196,9 @@ struct x86_pmu_capability { * Fixed-purpose performance events: */ +/* RDPMC offset for Fixed PMCs */ +#define INTEL_PMC_FIXED_RDPMC_BASE (1 << 30) + /* * All the fixed-mode PMCs are configured via this single MSR: */
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