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    Subject[PATCH V7 02/14] perf/x86/intel: Name the global status bit in NMI handler
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    Magic numbers are used in the current NMI handler for the global status
    bit. Use a meaningful name to replace the magic numbers to improve the
    readability of the code.

    Remove a Tab for all GLOBAL_STATUS_* and INTEL_PMC_IDX_FIXED_BTS macros
    to reduce the length of the line.

    Suggested-by: Peter Zijlstra <peterz@infradead.org>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    ---
    arch/x86/events/intel/core.c | 4 ++--
    arch/x86/include/asm/perf_event.h | 22 ++++++++++++----------
    2 files changed, 14 insertions(+), 12 deletions(-)

    diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
    index 50963472ee85..ac1408fe1aee 100644
    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -2389,7 +2389,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
    /*
    * PEBS overflow sets bit 62 in the global status register
    */
    - if (__test_and_clear_bit(62, (unsigned long *)&status)) {
    + if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
    u64 pebs_enabled = cpuc->pebs_enabled;

    handled++;
    @@ -2410,7 +2410,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status)
    /*
    * Intel PT
    */
    - if (__test_and_clear_bit(55, (unsigned long *)&status)) {
    + if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
    handled++;
    if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
    perf_guest_cbs->handle_intel_pt_intr))
    diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
    index 0c1b13720525..fd3eba65337f 100644
    --- a/arch/x86/include/asm/perf_event.h
    +++ b/arch/x86/include/asm/perf_event.h
    @@ -225,16 +225,18 @@ struct x86_pmu_capability {
    * values are used by actual fixed events and higher values are used
    * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
    */
    -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
    -
    -#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
    -#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
    -#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
    -#define GLOBAL_STATUS_ASIF BIT_ULL(60)
    -#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
    -#define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
    -#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
    -#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
    +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
    +
    +#define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
    +#define GLOBAL_STATUS_BUFFER_OVF_BIT 62
    +#define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
    +#define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
    +#define GLOBAL_STATUS_ASIF BIT_ULL(60)
    +#define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
    +#define GLOBAL_STATUS_LBRS_FROZEN_BIT 58
    +#define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
    +#define GLOBAL_STATUS_TRACE_TOPAPMI_BIT 55
    +#define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)

    /*
    * We model guest LBR event tracing as another fixed-mode PMC like BTS.
    --
    2.17.1
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