Messages in this thread | | | Subject | Re: [PATCH v4 2/4] iommu/arm-smmu: Workaround for Marvell Armada-AP806 SoC erratum #582743 | From | Tomasz Nowicki <> | Date | Thu, 16 Jul 2020 09:24:58 +0200 |
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On 15.07.2020 12:32, Robin Murphy wrote: > On 2020-07-15 08:06, Tomasz Nowicki wrote: >> From: Hanna Hawa <hannah@marvell.com> >> >> Due to erratum #582743, the Marvell Armada-AP806 can't access 64bit to >> ARM SMMUv2 registers. >> >> Provide implementation relevant hooks: >> - split the writeq/readq to two accesses of writel/readl. >> - mask the MMU_IDR2.PTFSv8 fields to not use AArch64 format (but >> only AARCH32_L) since with AArch64 format 32 bits access is not >> supported. >> >> Note that most 64-bit registers like TTBRn can be accessed as two 32-bit >> halves without issue, and AArch32 format ensures that the register writes >> which must be atomic (for TLBI etc.) need only be 32-bit. > > Thanks Tomasz, this has ended up as clean as I'd hoped it could, and > there's still room to come back and play more complicated games later if > a real need for AARCH64_64K at stage 2 crops up.
Based on your implementation infrastructure rework, indeed the code looks much cleaner :)
> > Reviewed-by: Robin Murphy <robin.murphy@arm.com> >
Thanks!
Tomasz
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