Messages in this thread | | | Date | Fri, 19 Jun 2020 20:31:02 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH 09/21] perf/x86: Expose CPUID enumeration bits for arch LBR |
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On Fri, Jun 19, 2020 at 07:03:57AM -0700, kan.liang@linux.intel.com wrote:
> + union { > + struct { > + /* Supported LBR depth values */ > + unsigned int arch_lbr_depth_mask:8; > + > + unsigned int reserved:22; > + > + /* Deep C-state Reset */ > + unsigned int arch_lbr_deep_c_reset:1; > + > + /* IP values contain LIP */ > + unsigned int arch_lbr_lip:1; > + }; > + unsigned int arch_lbr_eax; > + }; > + union { > + struct { > + /* CPL Filtering Supported */ > + unsigned int arch_lbr_cpl:1; > + > + /* Branch Filtering Supported */ > + unsigned int arch_lbr_filter:1; > + > + /* Call-stack Mode Supported */ > + unsigned int arch_lbr_call_stack:1; > + }; > + unsigned int arch_lbr_ebx; > + }; > + union { > + struct { > + /* Mispredict Bit Supported */ > + unsigned int arch_lbr_mispred:1; > + > + /* Timed LBRs Supported */ > + unsigned int arch_lbr_timed_lbr:1; > + > + /* Branch Type Field Supported */ > + unsigned int arch_lbr_br_type:1; > + }; > + unsigned int arch_lbr_ecx; > + };
Please, union cpuid28_e[abc]x in asm/perf_event.h right along with the existing cpuid10_e*x unions.
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