Messages in this thread Patch in this message | | | From | Tiezhu Yang <> | Subject | [PATCH v2] MIPS: Limit check_bugs32() to affected platform | Date | Fri, 10 Apr 2020 11:20:59 +0800 |
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In the current code, check_bugs32() only handles MIPS32 CPU type CPU_34K, it is better to build and call it on the affected platform.
Move check_bugs32() to the new added 34k-bugs32.c to indicate the fact that the code is specific to the 34k CPU, and also add CONFIG_CPU_34K_BUGS32 to control whether or not check the bugs.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> ---
v2: - Add new 34k-bugs32.c - Rename check_errata() to check_errata32() - Add CONFIG_CPU_34K_BUGS32 - Modify commit message
arch/mips/Kconfig | 4 ++++ arch/mips/include/asm/bugs.h | 4 +++- arch/mips/kernel/34k-bugs32.c | 29 +++++++++++++++++++++++++++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/cpu-probe.c | 25 ------------------------- 5 files changed, 37 insertions(+), 26 deletions(-) create mode 100644 arch/mips/kernel/34k-bugs32.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a1f973c..d95dc18 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2619,6 +2619,10 @@ config CPU_R4X00_BUGS64 bool default y if SYS_HAS_CPU_R4X00 && 64BIT && (TARGET_ISA_REV < 1) +config CPU_34K_BUGS32 + bool + default y if CPU_MIPS32_R2 + config MIPS_ASID_SHIFT int default 6 if CPU_R3000 || CPU_TX39XX diff --git a/arch/mips/include/asm/bugs.h b/arch/mips/include/asm/bugs.h index d72dc6e..bbf843a 100644 --- a/arch/mips/include/asm/bugs.h +++ b/arch/mips/include/asm/bugs.h @@ -35,7 +35,9 @@ static inline void check_bugs(void) unsigned int cpu = smp_processor_id(); cpu_data[cpu].udelay_val = loops_per_jiffy; - check_bugs32(); + + if (IS_ENABLED(CONFIG_CPU_34K_BUGS32)) + check_bugs32(); if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) check_bugs64(); diff --git a/arch/mips/kernel/34k-bugs32.c b/arch/mips/kernel/34k-bugs32.c new file mode 100644 index 0000000..dc3ac01 --- /dev/null +++ b/arch/mips/kernel/34k-bugs32.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +#include <asm/cpu.h> +#include <asm/cpu-info.h> +#include <asm/cpu-type.h> +#include <asm/bugs.h> + +static inline void check_errata32(void) +{ + struct cpuinfo_mips *c = ¤t_cpu_data; + + switch (current_cpu_type()) { + case CPU_34K: + /* + * Erratum "RPS May Cause Incorrect Instruction Execution" + * This code only handles VPE0, any SMP/RTOS code + * making use of VPE1 will be responsable for that VPE. + */ + if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) + write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); + break; + default: + break; + } +} + +void __init check_bugs32(void) +{ + check_errata32(); +} diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index d6e97df..c2fd191 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_PROC_FS) += proc.o obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o obj-$(CONFIG_CPU_R4X00_BUGS64) += r4k-bugs64.o +obj-$(CONFIG_CPU_34K_BUGS32) += 34k-bugs32.o obj-$(CONFIG_I8253) += i8253.o diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index f21a230..7179787 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -14,7 +14,6 @@ #include <linux/stddef.h> #include <linux/export.h> -#include <asm/bugs.h> #include <asm/cpu.h> #include <asm/cpu-features.h> #include <asm/cpu-type.h> @@ -461,30 +460,6 @@ static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c) c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS; } -static inline void check_errata(void) -{ - struct cpuinfo_mips *c = ¤t_cpu_data; - - switch (current_cpu_type()) { - case CPU_34K: - /* - * Erratum "RPS May Cause Incorrect Instruction Execution" - * This code only handles VPE0, any SMP/RTOS code - * making use of VPE1 will be responsable for that VPE. - */ - if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) - write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); - break; - default: - break; - } -} - -void __init check_bugs32(void) -{ - check_errata(); -} - /* * Probe whether cpu has config register by trying to play with * alternate cache bit and see whether it matters. -- 2.1.0
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