Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH v2 3/4] arch/x86: Optionally flush L1D on context switch | Date | Wed, 08 Apr 2020 01:52:30 +0200 |
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Balbir,
Balbir Singh <sblbir@amazon.com> writes: > diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h > index 6f66d841262d..69e6ea20679c 100644 > --- a/arch/x86/include/asm/tlbflush.h > +++ b/arch/x86/include/asm/tlbflush.h > @@ -172,7 +172,7 @@ struct tlb_state { > /* Last user mm for optimizing IBPB */ > union { > struct mm_struct *last_user_mm; > - unsigned long last_user_mm_ibpb; > + unsigned long last_user_mm_spec;
> -static inline unsigned long mm_mangle_tif_spec_ib(struct task_struct *next) > +static inline unsigned long mm_mangle_tif_spec_bits(struct task_struct *next)
> -static void cond_ibpb(struct task_struct *next) > +static void cond_mitigation(struct task_struct *next) > { > + unsigned long prev_mm, next_mm; > + > if (!next || !next->mm) > return;
can you please split out these preparatory changes into a separate patch?
Thanks,
tglx
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