Messages in this thread | | | Subject | Re: [RFC PATCH v10 6/9] media: tegra: Add Tegra210 Video input driver | From | Sowjanya Komatineni <> | Date | Sat, 25 Apr 2020 16:19:47 -0700 |
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On 4/25/20 4:13 PM, Dmitry Osipenko wrote: > External email: Use caution opening links or attachments > > > 24.04.2020 06:55, Sowjanya Komatineni пишет: >> +static int __maybe_unused vi_runtime_resume(struct device *dev) >> +{ >> + struct tegra_vi *vi = dev_get_drvdata(dev); >> + int ret; >> + >> + ret = regulator_enable(vi->vdd); >> + if (ret) { >> + dev_err(dev, "failed to enable VDD supply: %d\n", ret); >> + return ret; >> + } >> + >> + ret = clk_set_rate(vi->clk, vi->soc->vi_max_clk_hz); >> + if (ret) { >> + dev_err(dev, "failed to set vi clock rate: %d\n", ret); >> + goto disable_vdd; >> + } > Isn't setting clock rate using assigned-clocks in a device-tree enough? > Could you please clarify why this vi_max_clk_hz is needed?
Max clock rate with sensor support will be 998Mhz.
Later when sensor support is added, based on TPG or Sensor mode clock rate will be set here
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