Messages in this thread Patch in this message | | | From | Cong Zhang <> | Subject | [PATCH] ARM: align the start and end of v7_setup_stack to cache line | Date | Mon, 20 Apr 2020 22:50:35 +0800 |
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The v7_setup_stack is used when D-cache disabled. When CPU is reading something nearby with D-cache enabled. It is possible to read v7_setup_stack to cache line. There is a risk that when cache line write back the data, v7_setup_stack may already been modified by other CPU with D-cache disabled. The change make v7_setup_stack align cache line size and use the whole cache line to prevent corrupting v7_setup_stack.
Signed-off-by: Cong Zhang <congzhan@codeaurora.org> --- arch/arm/mm/proc-v7.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 339eb17..587e2eb 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -18,6 +18,7 @@ #include <asm/pgtable-hwdef.h> #include <asm/pgtable.h> #include <asm/memory.h> +#include <asm/cache.h> #include "proc-macros.S" @@ -548,10 +549,10 @@ __v7_setup_stack_ptr: ENDPROC(__v7_setup) .bss - .align 2 + .align L1_CACHE_SHIFT __v7_setup_stack: .space 4 * 7 @ 7 registers - + .align L1_CACHE_SHIFT __INITDATA .weak cpu_v7_bugs_init -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
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