Messages in this thread | | | From | Thomas Gleixner <> | Subject | Re: [PATCH 2/3] x86/split_lock: Bits in IA32_CORE_CAPABILITIES are not architectural | Date | Sat, 18 Apr 2020 11:27:24 +0200 |
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Xiaoyao,
can you please trim your replies?
Xiaoyao Li <xiaoyao.li@intel.com> writes: > On 4/18/2020 5:07 AM, Thomas Gleixner wrote: >> + * Bits in the IA32_CORE_CAPABILITIES are not architectural, so they should >> + * only be trusted if it is confirmed that a CPU model implements a >> + * specific feature at a particular bit position. >> + * >> + * The possible driver data field values: >> + * >> + * - 0: CPU models that are known to have the per-core split-lock detection >> + * feature even though they do not enumerate IA32_CORE_CAPABILITIES. >> + * >> + * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use >> + * bit 5 to enumerate the per-core split-lock detection feature. > > So now, it's tightly associated with CPU model, which makes it harder to > expose this feature to guest. For guest, the CPU model can be configured > to anything. > > As suggested by Sean internally, we'd better use a KVM CPUID to expose > it to guest, which makes it independent of CPU model.
Works for me.
Thanks,
tglx
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