Messages in this thread Patch in this message | | | From | Rémi Denis-Courmont <> | Subject | [PATCH 1/3] arm64: clean up trampoline vector loads | Date | Mon, 16 Mar 2020 14:40:44 +0200 |
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From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
This switches from custom instruction patterns to the regular large memory model sequence with ADRP and LDR. In doing so, the ADD instruction can be eliminated in the SDEI handler, and the code no longer assumes that the trampoline vectors and the vectors address both start on a page boundary.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> --- arch/arm64/kernel/entry.S | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index e5d4e30ee242..24f828739696 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -805,9 +805,9 @@ alternative_else_nop_endif 2: tramp_map_kernel x30 #ifdef CONFIG_RANDOMIZE_BASE - adr x30, tramp_vectors + PAGE_SIZE + adrp x30, tramp_vectors + PAGE_SIZE alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 - ldr x30, [x30] + ldr x30, [x30, #:lo12:__entry_tramp_data_start] #else ldr x30, =vectors #endif @@ -953,9 +953,8 @@ SYM_CODE_START(__sdei_asm_entry_trampoline) 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] #ifdef CONFIG_RANDOMIZE_BASE - adr x4, tramp_vectors + PAGE_SIZE - add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler - ldr x4, [x4] + adrp x4, tramp_vectors + PAGE_SIZE + ldr x4, [x4, #:lo12:__sdei_asm_trampoline_next_handler] #else ldr x4, =__sdei_asm_handler #endif -- 2.25.1
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