Messages in this thread | | | Subject | Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus | From | Roger Quadros <> | Date | Wed, 11 Mar 2020 09:20:05 +0200 |
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On 10/03/2020 17:48, Tony Lindgren wrote: > * Tero Kristo <t-kristo@ti.com> [200310 14:46]: >> On 10/03/2020 13:53, Roger Quadros wrote: >>> The L3 interconnect can access only 32-bits of address. >>> Add the dma-ranges property to reflect this limit. >>> >>> This will ensure that no device under L3 is >>> given > 32-bit address for DMA. >>> >>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM >>> and CONFIG_ARM_LPAE enabled. This is because the controller >>> can perform 64-bit DMA and was setting the dma_mask to 64-bit. >>> >>> Setting the correct bus_dma_limit fixes the issue. >> >> This seems kind of messy to modify almost every DT node because of this.... >> Are you sure this is the only way to get it done? No way to modify the sata >> node only which is impacted somehow? >> >> Also, what if you just pass 0xffffffff to the dma-ranges property? That >> would avoid modifying every node I guess. > > Also, I think these interconnects are not limited to 32-bit access.
But from Table 2-1. L3_MAIN Memory Map
Start address 0x0000_0000 End address 0xFFFF_FFFF
So it is 32-bit limit, right?
> So yeah I too would prefer a top level dma-ranges property assuming > that works. > > I guess there dma-ranges should not be 0xffffffff though if > limited to 2GB :) > > Regards, > > Tony >
-- cheers, -roger Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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