Messages in this thread | | | Subject | Re: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus | From | Robin Murphy <> | Date | Tue, 10 Mar 2020 16:16:14 +0000 |
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On 10/03/2020 3:48 pm, Tony Lindgren wrote: > * Tero Kristo <t-kristo@ti.com> [200310 14:46]: >> On 10/03/2020 13:53, Roger Quadros wrote: >>> The L3 interconnect can access only 32-bits of address. >>> Add the dma-ranges property to reflect this limit. >>> >>> This will ensure that no device under L3 is >>> given > 32-bit address for DMA. >>> >>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM >>> and CONFIG_ARM_LPAE enabled. This is because the controller >>> can perform 64-bit DMA and was setting the dma_mask to 64-bit. >>> >>> Setting the correct bus_dma_limit fixes the issue. >> >> This seems kind of messy to modify almost every DT node because of this.... >> Are you sure this is the only way to get it done? No way to modify the sata >> node only which is impacted somehow? >> >> Also, what if you just pass 0xffffffff to the dma-ranges property? That >> would avoid modifying every node I guess. > > Also, I think these interconnects are not limited to 32-bit access. > So yeah I too would prefer a top level dma-ranges property assuming > that works. > > I guess there dma-ranges should not be 0xffffffff though if > limited to 2GB :)
It should work fine to just describe the Q3 and Q4 DDR regions as the DMA range, i.e.:
ocp { ... dma-ranges = <0x80000000 0 0x80000000 0x80000000>; ... };
That would certainly be far less invasive :)
Robin.
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