Messages in this thread Patch in this message | | | From | Jesse Brandeburg <> | Subject | [PATCH v5 1/2] x86: fix bitops.h warning with a moved cast | Date | Mon, 24 Feb 2020 14:50:19 -0800 |
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Fix many sparse warnings when building with C=1.
When the kernel is compiled with C=1, there are lots of messages like: arch/x86/include/asm/bitops.h:77:37: warning: cast truncates bits from constant value (ffffff7f becomes 7f)
CONST_MASK() is using a signed integer "1" to create the mask which is later cast to (u8) when used, in order to yield an 8-bit value for the assembly instructions to use. Simplify the expressions used to clearly indicate they are working on 8-bit values only, which still keeps sparse happy without an accidental promotion to a 32 bit integer.
The reason the warning was occurring is because certain bitmasks that end with a mask next to a natural boundary like 7, 15, 23, 31, end up with a mask like 0x7f, which then results in sign extension when doing an invert (but I'm not a compiler expert). It was really only "clear_bit" that was having problems, and it was only on bit checks next to a byte boundary (top bit).
Verified with a test module (see next patch) and assembly inspection that the patch doesn't introduce any change in generated code.
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com> --- v5: changed code to use simple AND and XOR, updated commit message v4: reverse argument order as suggested by David Laight, added reviewed-by v3: Clean up the header file changes as per peterz. v2: use correct CC: list --- arch/x86/include/asm/bitops.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h index 062cdecb2f24..53f246e9df5a 100644 --- a/arch/x86/include/asm/bitops.h +++ b/arch/x86/include/asm/bitops.h @@ -54,7 +54,7 @@ arch_set_bit(long nr, volatile unsigned long *addr) if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "orb %1,%0" : CONST_MASK_ADDR(nr, addr) - : "iq" ((u8)CONST_MASK(nr)) + : "iq" (CONST_MASK(nr) & 0xff) : "memory"); } else { asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" @@ -74,7 +74,7 @@ arch_clear_bit(long nr, volatile unsigned long *addr) if (__builtin_constant_p(nr)) { asm volatile(LOCK_PREFIX "andb %1,%0" : CONST_MASK_ADDR(nr, addr) - : "iq" ((u8)~CONST_MASK(nr))); + : "iq" (CONST_MASK(nr) ^ 0xff)); } else { asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0" : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); base-commit: ca7e1fd1026c5af6a533b4b5447e1d2f153e28f2 -- 2.24.1
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