Messages in this thread Patch in this message | | | From | Wolfram Sang <> | Subject | [PATCH 6/6] WIP: arm64: dts: renesas: falcon: switch to from SCIF0 to HSCIF0 | Date | Mon, 28 Dec 2020 12:27:13 +0100 |
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Mainly for testing the HSCIF0 node. We could make this switch permanent, but we never did for any other SoC. So, I think this is not to be applied.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index 54763c73dc74..e2bbaa7a72e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -14,7 +14,7 @@ / { compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0"; aliases { - serial0 = &scif0; + serial0 = &hscif0; }; chosen { @@ -352,9 +352,9 @@ mmc_pins: mmc { power-source = <1800>; }; - scif0_pins: scif0 { - groups = "scif0_data", "scif0_ctrl"; - function = "scif0"; + hscif0_pins: hscif0 { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; }; scif_clk_pins: scif_clk { @@ -369,7 +369,11 @@ &rwdt { }; &scif0 { - pinctrl-0 = <&scif0_pins>; + status = "disabled"; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; pinctrl-names = "default"; uart-has-rtscts; -- 2.29.2
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