Messages in this thread | | | Subject | Re: [PATCH] clk: mvebu: a3700: fix the XTAL MODE pin to MPP1_9 | From | Stephen Boyd <> | Date | Sun, 20 Dec 2020 17:47:17 -0800 |
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Quoting Pali Rohár (2020-12-20 08:21:35) > On Saturday 19 December 2020 15:51:30 Stephen Boyd wrote: > > Quoting Pali Rohár (2020-11-06 02:00:39) > > > From: Terry Zhou <bjzhou@marvell.com> > > > > > > There is an error in the current code that the XTAL MODE > > > pin was set to NB MPP1_31 which should be NB MPP1_9. > > > The latch register of NB MPP1_9 has different offset of 0x8. > > > > > > Signed-off-by: Terry Zhou <bjzhou@marvell.com> > > > [pali: Fix pin name in commit message] > > > Signed-off-by: Pali Rohár <pali@kernel.org> > > > Fixes: 7ea8250406a6 ("clk: mvebu: Add the xtal clock for Armada 3700 SoC") > > > Cc: stable@vger.kernel.org > > > > > > --- > > > > Applied to clk-next > > Hello Stephen! As this is fix also for stable releases, could you please > queue this patch for 5.11 release?
No problem.
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