Messages in this thread Patch in this message | | | Date | Tue, 14 Jan 2020 14:23:55 +0000 | From | Krzysztof Piecuch <> | Subject | [PATCH] x86/tsc: Add tsc_guess flag disabling CPUID.16h use for tsc calibration |
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Changing base clock frequency directly impacts tsc hz but not CPUID.16h values. An overclocked CPU supporting CPUID.16h and partial CPUID.15h support will set tsc hz according to "best guess" given by CPUID.16h relying on tsc_refine_calibration_work to give better numbers later. tsc_refine_calibration_work will refuse to do its work when the outcome is off the early tsc hz value by more than 1% which is certain to happen on an overclocked system.
Signed-off-by: Krzysztof Piecuch <piecuch@protonmail.com> --- Documentation/admin-guide/kernel-parameters.txt | 6 ++++++ arch/x86/kernel/tsc.c | 12 ++++++++++-- 2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index ade4e6ec23e0..54ae9e153a19 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4905,6 +4905,12 @@ interruptions from clocksource watchdog are not acceptable).
+ tsc_guess= [X86,INTEL] Don't use data provided by CPUID.16h during + early tsc calibration. Disabling this may be useful for + CPUs with altered base clocks. + Format: <bool> (1/Y/y=enable, 0/N/n=disable) + default: enabled + tsx= [X86] Control Transactional Synchronization Extensions (TSX) feature in Intel processors that support TSX control. diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 7e322e2daaf5..a807c33a3d41 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -59,6 +59,13 @@ struct cyc2ns {
static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
+static bool _read_mostly tsc_guess = 1; +static int __init tsc_guess_setup(char *buf) +{ + return strtobool(buf, &tsc_guess); +} +early_param("tsc_guess", tsc_guess_setup); + __always_inline void cyc2ns_read_begin(struct cyc2ns_data *data) { int seq, idx; @@ -654,7 +661,8 @@ unsigned long native_calibrate_tsc(void) * clock, but we can easily calculate it to a high degree of accuracy * by considering the crystal ratio and the CPU speed. */ - if (crystal_khz == 0 && boot_cpu_data.cpuid_level >= 0x16) { + if (crystal_khz == 0 && tsc_guess && + boot_cpu_data.cpuid_level >= 0x16) { unsigned int eax_base_mhz, ebx, ecx, edx;
cpuid(0x16, &eax_base_mhz, &ebx, &ecx, &edx); @@ -692,7 +700,7 @@ static unsigned long cpu_khz_from_cpuid(void) if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) return 0;
- if (boot_cpu_data.cpuid_level < 0x16) + if (boot_cpu_data.cpuid_level < 0x16 || !tsc_guess) return 0;
eax_base_mhz = ebx_max_mhz = ecx_bus_mhz = edx = 0; -- 2.20.1
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