Messages in this thread Patch in this message | | | From | Jiaxun Yang <> | Subject | [PATCH 1/2] MIPS: Define pgprot_dmacoherent according to coherentio status | Date | Mon, 13 Jan 2020 22:07:04 +0800 |
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For MIPS chips that support coherentio DMA, it's always safe to make DMA requests cached.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/include/asm/dma-coherence.h | 14 ++++++++++++++ arch/mips/kernel/setup.c | 1 + 2 files changed, 15 insertions(+)
diff --git a/arch/mips/include/asm/dma-coherence.h b/arch/mips/include/asm/dma-coherence.h index 5eaa1fcc878a..bc0df7684cae 100644 --- a/arch/mips/include/asm/dma-coherence.h +++ b/arch/mips/include/asm/dma-coherence.h @@ -9,6 +9,8 @@ #ifndef __ASM_DMA_COHERENCE_H #define __ASM_DMA_COHERENCE_H +#include <asm/pgtable.h> + enum coherent_io_user_state { IO_COHERENCE_DEFAULT, IO_COHERENCE_ENABLED, @@ -35,4 +37,16 @@ static inline bool dev_is_dma_coherent(struct device *dev) #define hw_coherentio 0 #endif /* CONFIG_DMA_MAYBE_COHERENT */ +#if !defined(CONFIG_DMA_PERDEV_COHERENT) +#define pgprot_dmacoherent pgprot_dmacoherent +static inline pgprot_t pgprot_dmacoherent(pgprot_t prot) +{ + if (coherentio == IO_COHERENCE_ENABLED || + (coherentio == IO_COHERENCE_DEFAULT && hw_coherentio)) + return prot; + + return pgprot_noncached(prot); +} +#endif + #endif diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 701f4bc3046f..01f725819df7 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -831,6 +831,7 @@ arch_initcall(debugfs_mips); enum coherent_io_user_state coherentio = IO_COHERENCE_DEFAULT; EXPORT_SYMBOL_GPL(coherentio); int hw_coherentio = 0; /* Actual hardware supported DMA coherency setting. */ +EXPORT_SYMBOL_GPL(hw_coherentio); static int __init setcoherentio(char *str) { -- 2.24.1
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