Messages in this thread | | | Date | Thu, 19 Sep 2019 13:22:16 +0200 | From | Uwe Kleine-König <> | Subject | Re: [PATCH v2] serial: imx: adapt rx buffer and dma periods |
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On Thu, Sep 19, 2019 at 12:26:28PM +0200, Philipp Puschmann wrote: > Using only 4 DMA periods for UART RX is very few if we have a high > frequency of small transfers - like in our case using Bluetooth with > many small packets via UART - causing many dma transfers but in each > only filling a fraction of a single buffer. Such a case may lead to > the situation that DMA RX transfer is triggered but no free buffer is > available. While we have addressed the dma handling already with > "dmaengine: imx-sdma: fix dma freezes" we still want to avoid
Is this statement still true now that you split this patch out of your bigger series?
> UART RX FIFO overrun. So we decrease the size of the buffers and > increase their number and the total buffer size.
What happens when such an RX FIFO overrun happens? Are characters lost? Or only time? Does your change have an influence if I do fewer but bigger transfers?
Best regards Uwe
-- Pengutronix e.K. | Uwe Kleine-König | Industrial Linux Solutions | http://www.pengutronix.de/ |
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