Messages in this thread | | | From | Neil Armstrong <> | Subject | [PATCH 0/3] clk: meson: g12a: fixes for DVFS | Date | Thu, 19 Sep 2019 11:36:24 +0200 |
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This is the first serie of fixes for DVFS support on G12a: - Patch 1 fixes a rebase issue where a CLK_SET_RATE_NO_REPARENT appeared on the wrong clock and a SET_RATE_PARENT went missing - Patch 2 helps CCF use the right clock tree for the sub 1GHz clock range - Patch 3 fixes an issue when we enter suspend with a non-SYS_PLL CPU clock, leading to a SYS_PLL never enabled again
Neil Armstrong (3): clk: meson: g12a: fix cpu clock rate setting clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes clk: meson: clk-pll: always enable a critical PLL when setting the rate
drivers/clk/meson/clk-pll.c | 2 +- drivers/clk/meson/g12a.c | 13 +++++++++++-- 2 files changed, 12 insertions(+), 3 deletions(-)
-- 2.22.0
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