Messages in this thread Patch in this message | | | From | kan.liang@linux ... | Subject | [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for TOPDOWN.SLOTS | Date | Mon, 26 Aug 2019 07:47:33 -0700 |
| |
From: Kan Liang <kan.liang@linux.intel.com>
TOPDOWN.SLOTS(0x0400) is not a generic event. It is only available on fixed counter3.
Don't extend its mask to generic counters.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/intel/core.c | 6 ++++-- arch/x86/include/asm/perf_event.h | 5 +++++ 2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 9e911a96972b..1b2c37ed49db 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5081,12 +5081,14 @@ __init int intel_pmu_init(void) if (x86_pmu.event_constraints) { /* - * event on fixed counter2 (REF_CYCLES) only works on this + * event on fixed counter2 (REF_CYCLES) and + * fixed counter3 (TOPDOWN.SLOTS) only work on this * counter, so do not extend mask to generic counters */ for_each_event_constraint(c, x86_pmu.event_constraints) { if (c->cmask == FIXED_EVENT_FLAGS - && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { + && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES + && c->idxmsk64 != INTEL_PMC_MSK_FIXED_SLOTS) { c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; } c->idxmsk64 &= diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 1392d5e6e8d6..457d35a75ad3 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -167,6 +167,11 @@ struct x86_pmu_capability { #define INTEL_PMC_IDX_FIXED_REF_CYCLES (INTEL_PMC_IDX_FIXED + 2) #define INTEL_PMC_MSK_FIXED_REF_CYCLES (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES) +/* TOPDOWN.SLOTS: */ +#define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c +#define INTEL_PMC_IDX_FIXED_SLOTS (INTEL_PMC_IDX_FIXED + 3) +#define INTEL_PMC_MSK_FIXED_SLOTS (1ULL << INTEL_PMC_IDX_FIXED_SLOTS) + /* * We model BTS tracing as another fixed-mode PMC. * -- 2.17.1
| |