Messages in this thread | | | Date | Tue, 9 Jul 2019 08:35:40 -0500 | From | Segher Boessenkool <> | Subject | Re: [PATCH v2] powerpc: slightly improve cache helpers |
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On Tue, Jul 09, 2019 at 07:04:43AM +0200, Christophe Leroy wrote: > Le 08/07/2019 à 21:14, Nathan Chancellor a écrit : > >On Mon, Jul 08, 2019 at 11:19:30AM +1000, Michael Ellerman wrote: > >>On Fri, 2019-05-10 at 09:24:48 UTC, Christophe Leroy wrote: > >>>Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers > >>>that are summed to obtain the target address. Using 'Z' constraint > >>>and '%y0' argument gives GCC the opportunity to use both registers > >>>instead of only one with the second being forced to 0. > >>> > >>>Suggested-by: Segher Boessenkool <segher@kernel.crashing.org> > >>>Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > >> > >>Applied to powerpc next, thanks. > >> > >>https://git.kernel.org/powerpc/c/6c5875843b87c3adea2beade9d1b8b3d4523900a > >> > >>cheers > > > >This patch causes a regression with clang: > > Is that a Clang bug ?
I would think so, but cannot tell from the given information.
> Do you have a disassembly of the code both with and without this patch > in order to compare ?
That's what we need to start debugging this, yup.
> Segher, any idea ?
There is nothing I recognise, no.
Segher
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