Messages in this thread Patch in this message | | | From | "Kirill A. Shutemov" <> | Subject | [PATCH] x86/asm: Add support for MOVDIR64B instruction | Date | Wed, 31 Jul 2019 02:05:54 +0300 |
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Add support for a new instruction MOVDIR64B. The instruction moves 64-bytes as direct-store with 64-byte write atomicity from source memory address to destination memory address.
MOVDIR64B requires the destination address to be 64-byte aligned. No alignment restriction is enforced for source operand.
See Intel Software Developer’s Manual for more information on the instruction.
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> ---
Several upcoming patchsets will make use of the helper.
--- arch/x86/include/asm/special_insns.h | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/arch/x86/include/asm/special_insns.h b/arch/x86/include/asm/special_insns.h index 219be88a59d2..059e7bd331d2 100644 --- a/arch/x86/include/asm/special_insns.h +++ b/arch/x86/include/asm/special_insns.h @@ -248,6 +248,13 @@ static inline void clwb(volatile void *__p) #define nop() asm volatile ("nop") +static inline void movdir64b(void *dst, const void *src) +{ + /* movdir64b [rdx], rax */ + asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" + : "=m" (*(char *)dst) + : "d" (src), "a" (dst)); +} #endif /* __KERNEL__ */ -- 2.21.0
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