Messages in this thread | | | From | "Prakhya, Sai Praneeth" <> | Subject | RE: [PATCH 1/1] iommu/vt-d: Correctly check format of page table in debugfs | Date | Mon, 22 Jul 2019 05:21:37 +0000 |
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Hi Allen,
> diff --git a/drivers/iommu/intel-iommu-debugfs.c b/drivers/iommu/intel- > iommu-debugfs.c > index 73a552914455..e31c3b416351 100644 > --- a/drivers/iommu/intel-iommu-debugfs.c > +++ b/drivers/iommu/intel-iommu-debugfs.c > @@ -235,7 +235,7 @@ static void ctx_tbl_walk(struct seq_file *m, struct > intel_iommu *iommu, u16 bus) > tbl_wlk.ctx_entry = context; > m->private = &tbl_wlk; > > - if (pasid_supported(iommu) && is_pasid_enabled(context)) { > + if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & > DMA_RTADDR_SMT) {
Thanks for adding this, I do believe this is a good addition but I also think that we might need "is_pasid_enabled()" as well. It checks if PASIDE bit in context entry is enabled or not.
I am thinking that even though DMAR might be using scalable root and context table, the entry itself should have PASIDE bit set. Did I miss something here?
And I also think a macro would be better so that it could reused elsewhere (if need be).
Regards, Sai
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