Messages in this thread | | | Date | Wed, 1 May 2019 22:32:48 +0200 | From | Karsten Merker <> | Subject | Re: [PATCH] RISC-V: Add an Image header that boot loader can parse. |
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On Wed, May 01, 2019 at 09:54:43PM +0200, Karsten Merker wrote: > On Wed, May 01, 2019 at 10:41:52PM +0530, Anup Patel wrote: > > On Wed, May 1, 2019 at 10:30 PM Mark Rutland <mark.rutland@arm.com> wrote: > > > On Mon, Apr 29, 2019 at 10:42:40PM -0700, Atish Patra wrote: > > > > On 4/29/19 4:40 PM, Palmer Dabbelt wrote: > > > > > On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.patra@wdc.com wrote:
> Probably I'm missing something obvious, but I cannot completely > follow you here. My understanding is as follows: [...] > If the first byte in a PE/COFF header has to be an ASCII "M", > that is 01001101 in binary. RISC-V is little-endian and the last > two bits of the lowest-value byte define the type of instruction. > According to the chapter "Base Instruction-Length Encoding" in > the RISC-V ISA spec everything except 11 as the lowest bits > denotes a compressed instruction and if I have puzzeled together > the the various instruction bits correctly, ASCII "MZ" would be > excuted as a compressed load immediate to x9/s1, wouldn't it?
Sorry, I have misinterpreted a bitfield in the spec, it's indeed a compressed load immediate to x20/s4.
Regards, Karsten -- Ich widerspreche hiermit ausdrücklich der Nutzung sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der Werbung sowie der Markt- oder Meinungsforschung.
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