Messages in this thread | | | Date | Wed, 1 May 2019 21:54:43 +0200 | From | Karsten Merker <> | Subject | Re: [PATCH] RISC-V: Add an Image header that boot loader can parse. |
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On Wed, May 01, 2019 at 10:41:52PM +0530, Anup Patel wrote: > On Wed, May 1, 2019 at 10:30 PM Mark Rutland <mark.rutland@arm.com> wrote: > > On Mon, Apr 29, 2019 at 10:42:40PM -0700, Atish Patra wrote: > > > On 4/29/19 4:40 PM, Palmer Dabbelt wrote: > > > > On Tue, 23 Apr 2019 16:25:06 PDT (-0700), atish.patra@wdc.com wrote: > > > > > Currently, last stage boot loaders such as U-Boot can accept only > > > > > uImage which is an unnecessary additional step in automating boot flows. > > > > > > > > > > Add a simple image header that boot loaders can parse and directly > > > > > load kernel flat Image. The existing booting methods will continue to > > > > > work as it is. > > > > > > > > > > Tested on both QEMU and HiFive Unleashed using OpenSBI + U-Boot + Linux. > > > > > > > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > > > > --- > > > > > arch/riscv/include/asm/image.h | 32 ++++++++++++++++++++++++++++++++ > > > > > arch/riscv/kernel/head.S | 28 ++++++++++++++++++++++++++++ > > > > > 2 files changed, 60 insertions(+) > > > > > create mode 100644 arch/riscv/include/asm/image.h > > > > > > > > > > diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h > > > > > new file mode 100644 > > > > > index 000000000000..76a7e0d4068a > > > > > --- /dev/null > > > > > +++ b/arch/riscv/include/asm/image.h > > > > > @@ -0,0 +1,32 @@ > > > > > +/* SPDX-License-Identifier: GPL-2.0 */ > > > > > + > > > > > +#ifndef __ASM_IMAGE_H > > > > > +#define __ASM_IMAGE_H > > > > > + > > > > > +#define RISCV_IMAGE_MAGIC "RISCV" > > > > > + > > > > > +#ifndef __ASSEMBLY__ > > > > > +/* > > > > > + * struct riscv_image_header - riscv kernel image header > > > > > + * > > > > > + * @code0: Executable code > > > > > + * @code1: Executable code > > > > > + * @text_offset: Image load offset > > > > > + * @image_size: Effective Image size > > > > > + * @reserved: reserved > > > > > + * @magic: Magic number > > > > > + * @reserved: reserved > > > > > + */ > > > > > + > > > > > +struct riscv_image_header { > > > > > + u32 code0; > > > > > + u32 code1; > > > > > + u64 text_offset; > > > > > + u64 image_size; > > > > > + u64 res1; > > > > > + u64 magic; > > > > > + u32 res2; > > > > > + u32 res3; > > > > > +}; > > > > > > > > I don't want to invent our own file format. Is there a reason we can't just > > > > use something standard? Off the top of my head I can think of ELF files and > > > > multiboot. > > > > > > Additional header is required to accommodate PE header format. Currently, > > > this is only used for booti command but it will be reused for EFI headers as > > > well. Linux kernel Image can pretend as an EFI application if PE/COFF header > > > is present. This removes the need of an explicit EFI boot loader and EFI > > > firmware can directly load Linux (obviously after EFI stub implementation > > > for RISC-V). > > > > Adding the EFI stub on arm64 required very careful consideration of our > > Image header and the EFI spec, along with the PE/COFF spec. > > > > For example, to be a compliant PE/COFF header, the first two bytes of > > your kernel image need to be "MZ" in ASCII. On arm64 we happened to find > > a valid instruction that we could rely upon that met this requirement... > > The "MZ" ASCII (i.e. 0x5a4d) is "li s4,-13" instruction in RISC-V so this > modifies "s4" register which is pretty harmless from Linux RISC-V booting > perspective. > > Of course, we should only add "MZ" ASCII in Linux RISC-V image header > when CONFIG_EFI is enabled (just like Linux ARM64).
Probably I'm missing something obvious, but I cannot completely follow you here. My understanding is as follows:
The kernel gets executed by jumping to the _start label, where it currently immediately starts with setting up everything (mask interrupts, disable FPU, etc). Now we insert a structure before the actual init code where the first 64 bits of the structure (the code0 and code1 fields) are filled with values that constitute a valid jump opcode to the actual init code behind the end of the new structure.
If the first byte in a PE/COFF header has to be an ASCII "M", that is 01001101 in binary. RISC-V is little-endian and the last two bits of the lowest-value byte define the type of instruction. According to the chapter "Base Instruction-Length Encoding" in the RISC-V ISA spec everything except 11 as the lowest bits denotes a compressed instruction and if I have puzzeled together the the various instruction bits correctly, ASCII "MZ" would be excuted as a compressed load immediate to x9/s1, wouldn't it?
If my previous thoughts are correct, this would also mean that having a PE/COFF-compatible header for EFI boot would make a kernel image inherently incompatible with performing a non-EFI boot of the same image on systems that don't implement the C extension. As the work-in-progress RISC-V Unix platform spec will probably mandate C, that probably won't be much of a practical problem, though.
Regards, Karsten -- Ich widerspreche hiermit ausdrücklich der Nutzung sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der Werbung sowie der Markt- oder Meinungsforschung.
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