Messages in this thread | | | From | Paul Burton <> | Subject | Re: [RFC][PATCH 4/5] mips/atomic: Fix smp_mb__{before,after}_atomic() | Date | Wed, 24 Apr 2019 21:24:31 +0000 |
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Hi Peter,
On Wed, Apr 24, 2019 at 02:37:00PM +0200, Peter Zijlstra wrote: > --- a/arch/mips/include/asm/barrier.h > +++ b/arch/mips/include/asm/barrier.h > @@ -230,9 +238,6 @@ > #define nudge_writes() mb() > #endif > > -#define __smp_mb__before_atomic() __smp_mb__before_llsc() > -#define __smp_mb__after_atomic() smp_llsc_mb() > - > /* > * Some Loongson 3 CPUs have a bug wherein execution of a memory access (load, > * store or pref) in between an ll & sc can cause the sc instruction to
I think this bit should be part of patch 3, where you currently add a second definition of these 2 macros.
Otherwise this one looks reasonable to me.
Thanks, Paul
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