Messages in this thread | | | From | Linus Torvalds <> | Date | Thu, 25 Apr 2019 09:12:19 -0700 | Subject | Re: Re: [RFC][PATCH 2/5] mips/atomic: Fix loongson_llsc_mb() wreckage |
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On Wed, Apr 24, 2019 at 9:59 PM <huangpei@loongson.cn> wrote: > > In one word, the bug only affect local cpu‘s ll/sc operation, and affect MP system. > > If local_t is only ll/sc manipulated by current CPU, then no need fix it.
As to the whole MP vs UP issue:
Is this "guaranteed no problem on UP" true even in the presence of DMA? I'm _hoping_ some MIPS chips are starting to be coherent with DMA (but maybe DMA never participates in any coherency traffic that could trigger the bug even if the DMA _were_ to be coherent?).
Also, as Peter mentioned, we do depend on ll/sc also reacting to interrupts - again including on UP systems, of course. I assume that's always handled correctly, and that an interrupt will set the right state that the SC will not succeed?
Finally, it worries me a bit that the loongson_llsc_mb() things are all at the C level, so who knows what compiler behavior you'll see between the ll/sc inline asm, and the loongson_llsc_mb() generation. Hopefully not a lot (and presumably mostly just stack reloads etc that probably don't change any cache state), but I do wonder if the loongson quirk should be *inside* the asm rather than separate.
Linus
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