| From | Stephen Boyd <> | Subject | Re: [PATCH v5 7/9] clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data | Date | Thu, 11 Apr 2019 13:21:15 -0700 |
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Quoting Weiyi Lu (2019-03-04 21:05:44) > In previous MediaTek PLL design, it assumes the pcw change control > is always on the CON1 register. > However, the pcw change bit on MT8183 was moved onto CON0 because > the the PCW length of audio PLLs are extended to 32-bit. > Add configurable pcw_chg_reg to set the pcw change control register > address or using the default control register CON1 if without > setting in pll data. > > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> > ---
Applied to clk-next
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