Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v5 3/9] clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data | Date | Thu, 11 Apr 2019 13:14:42 -0700 |
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Quoting Nicolas Boichat (2019-03-07 22:20:27) > On Tue, Mar 5, 2019 at 1:06 PM Weiyi Lu <weiyi.lu@mediatek.com> wrote: > > > > From: Owen Chen <owen.chen@mediatek.com> > > > > 1. pcwibits: The integer bits of pcw for plls is extend to 8 bits, > > add a variable to indicate this change and > > backward-compatible. > > 2. fmin: The pll freqency lower-bound is vary from 1GMhz to > > Minor nit: frequency (Stephen I guess you could fix that when applying...)
What's a 1GMhz? Anyway, fixed the typo.
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