Messages in this thread | | | Date | Fri, 22 Mar 2019 18:08:41 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH V3 01/23] perf/x86: Support outputting XMM registers |
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On Fri, Mar 22, 2019 at 09:36:56AM -0700, kan.liang@linux.intel.com wrote: > From: Kan Liang <kan.liang@linux.intel.com> > > Starting from Icelake, XMM registers can be collected in PEBS record. > But current code only output the pt_regs. > > Add a new struct x86_perf_regs for both pt_regs and xmm_regs. > XMM registers are 128 bit. To simplify the code, they are handled like > two different registers, which means setting two bits in the register > bitmap. This also allows only sampling the lower 64bit bits in XMM. > The index of XMM registers starts from 32. There are 16 XMM registers. > So all reserved space for regs are used. > PERF_REG_X86_MAX stands for the max number of all x86 regs include XMM. > PERF_REG_GPR_X86_MAX stands for the max number of all x86 general > purpose registers, which not include XMM. > PERF_REG_GPR_X86_32_MAX and PERF_REG_GPR_X86_64_MAX are introduced to > replace PERF_REG_X86_32_MAX and PERF_REG_X86_64_MAX for x86 general > purpose registers. > > The REG_RESERVED is also updated to allow the XMM registers. > XMM is not supported on all platforms. Adding has_xmm_regs to indicate > the specific platform. Also add checks in x86_pmu_hw_config() to reject > invalid config of regs_user and regs_intr.
> diff --git a/arch/x86/include/uapi/asm/perf_regs.h b/arch/x86/include/uapi/asm/perf_regs.h > index f3329cabce5c..b33995313d17 100644 > --- a/arch/x86/include/uapi/asm/perf_regs.h > +++ b/arch/x86/include/uapi/asm/perf_regs.h > @@ -28,7 +28,29 @@ enum perf_event_x86_regs { > PERF_REG_X86_R14, > PERF_REG_X86_R15, > > - PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, > - PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
So this changes UAPI visible symbols... did we think about that?
> + /* These all need two bits set because they are 128bit */ > + PERF_REG_X86_XMM0 = 32, > + PERF_REG_X86_XMM1 = 34, > + PERF_REG_X86_XMM2 = 36, > + PERF_REG_X86_XMM3 = 38, > + PERF_REG_X86_XMM4 = 40, > + PERF_REG_X86_XMM5 = 42, > + PERF_REG_X86_XMM6 = 44, > + PERF_REG_X86_XMM7 = 46, > + PERF_REG_X86_XMM8 = 48, > + PERF_REG_X86_XMM9 = 50, > + PERF_REG_X86_XMM10 = 52, > + PERF_REG_X86_XMM11 = 54, > + PERF_REG_X86_XMM12 = 56, > + PERF_REG_X86_XMM13 = 58, > + PERF_REG_X86_XMM14 = 60, > + PERF_REG_X86_XMM15 = 62, > + > + /* This does not include the XMMX registers */ > + PERF_REG_GPR_X86_32_MAX = PERF_REG_X86_GS + 1, > + PERF_REG_GPR_X86_64_MAX = PERF_REG_X86_R15 + 1, > + > + /* All registers include the XMMX registers */ > + PERF_REG_X86_MAX = PERF_REG_X86_XMM15 + 2, > }; > #endif /* _ASM_X86_PERF_REGS_H */
Also, what happens if we run a 32bit kernel or 32bit compat task?
Then the register dump will report PERF_SAMPLE_REGS_ABI_32, should we then still interpret the XMM registers as 2x64bit?
Are they still at the same offset?
Do we need additional PERF_SAMPLE_REGS_ABI_* definitions for this?
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