Messages in this thread | | | Subject | Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs | From | Stephen Boyd <> | Date | Tue, 26 Nov 2019 10:01:17 -0800 |
| |
Quoting Joel Stanley (2019-11-25 16:59:19) > Hi Stephen, > > On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > > single gate for each MAC. > > > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > > > Reviewed-by: Joel Stanley <joel@jms.id.au> > > I noticed this one hasn't been applied to clk-next. >
It's marked awaiting upstream in my UI. I think it was some patch that might have come through your PR?
| |