Messages in this thread | ![/](/images/icornerl.gif) | | From | Joel Stanley <> | Date | Tue, 26 Nov 2019 00:59:19 +0000 | Subject | Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs |
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Hi Stephen,
On Thu, 10 Oct 2019 at 23:41, Joel Stanley <joel@jms.id.au> wrote: > > On Thu, 10 Oct 2019 at 02:06, Andrew Jeffery <andrew@aj.id.au> wrote: > > > > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > > single gate for each MAC. > > > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > > Reviewed-by: Joel Stanley <joel@jms.id.au>
I noticed this one hasn't been applied to clk-next.
Cheers,
Joel
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