Messages in this thread | | | From | Manfred Spraul <> | Subject | [PATCH 0/3] Clarify/standardize memory barriers for ipc | Date | Fri, 11 Oct 2019 13:20:04 +0200 |
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Hi,
Partially based on the findings from Waiman Long:
a) The memory barriers in ipc are not properly documented, and at least for some architectures insufficient: Reading the xyz->status is only a control barrier, thus smp_acquire__after_ctrl_dep() was missing in mqueue.c and msg.c sem.c contained a full smp_mb(), which is not required.
Patch 1: Document that wake_q_add() contains a barrier.
b) wake_q_add() provides a memory barrier, ipc/mqueue.c relies on this. Move the documentation to wake_q_add(), instead writing it in ipc/mqueue.c
Patch 2-4: Update the ipc code, especially add missing smp_mb__after_ctrl_dep().
c) [optional] Clarify that smp_mb__{before,after}_atomic() are compatible with all RMW atomic operations, not just the operations that do not return a value.
Patch 5: Documentation for smp_mb__{before,after}_atomic().
From my point of view, patch 1 is a prerequisite for patches 2-4: If the barrier is not part of the documented API, then ipc should not rely on it, i.e. then I would propose to replace the WRITE_ONCE with smp_store_release().
Open issues: - More testing. I did some tests, but doubt that the tests would be sufficient to show issues with regards to incorrect memory barriers.
- Should I add a "Fixes:" or "Cc:stable"? The only issues that I see are the missing smp_mb__after_ctrl_dep(), and WRITE_ONCE() vs. "ptr = NULL".
What do you think?
-- Manfred
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