Messages in this thread | | | From | "Tian, Kevin" <> | Subject | RE: [PATCH v2 06/12] iommu/vt-d: Add second level page table interface | Date | Thu, 13 Sep 2018 05:52:32 +0000 |
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> From: Raj, Ashok > Sent: Saturday, September 8, 2018 1:43 AM > > On Fri, Sep 07, 2018 at 10:47:11AM +0800, Lu Baolu wrote: > > > > >>+ > > >>+ intel_pasid_clear_entry(dev, pasid); > > >>+ > > >>+ if (!ecap_coherent(iommu->ecap)) { > > >>+ pte = intel_pasid_get_entry(dev, pasid); > > >>+ clflush_cache_range(pte, sizeof(*pte)); > > >>+ } > > >>+ > > >>+ pasid_based_pasid_cache_invalidation(iommu, did, pasid); > > >>+ pasid_based_iotlb_cache_invalidation(iommu, did, pasid); > > >>+ > > >>+ /* Device IOTLB doesn't need to be flushed in caching mode. */ > > >>+ if (!cap_caching_mode(iommu->cap)) > > >>+ pasid_based_dev_iotlb_cache_invalidation(iommu, dev, > > >>pasid); > > > > > >can you elaborate, or point to any spec reference? > > > > > > > In the driver, device iotlb doesn't get flushed in caching mode. I just > > follow what have been done there. > > > > It also makes sense to me since only the bare metal host needs to > > consider whether and how to flush the device iotlb. > > > > DavidW might remember, i think the idea was to help with cost > of virtualization, we can avoid taking 2 exits vs handling > it directly when we do iotlb flushing instead. >
OK, performance-wise it makes sense. though strictly speaking it doesn't follow spec...
Thanks Kevin
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