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Subject[PATCH v3 00/19] IOMMU: Tegra GART driver clean up and optimization

In the previous iteration Thierry Reding suggested that it is better to
break/change GART's device-tree ABI in order to integrate it with Memory
Controller without much churning. So this series now includes the device
tree changes.

After making GART to disallow more than one active IOMMU domain at a time,
I realized that the domain clients managing code has a few significant bugs
and now they are fixed. During the bugs squashing, I found that drivers code
require a major cleanup and hence there are now couple more patches that make
the code less tangled and easier to maintain as a result.


v3: Memory Controller integration part has been reworked and now GART's
device-tree binding is changed. Adding Rob Herring for the device-tree
changes reviewing.

GART now disallows more than one active domain at a time.

Fixed "spinlock recursion", "NULL pointer dereference" and "detaching
of all devices from inactive domains".

New code-refactoring patches.

The previously standalone patch "memory: tegra: Don't invoke Tegra30+
specific memory timing setup on Tegra20" is now included into this
series because there is a dependency on that patch and it wasn't applied

v2: Addressed review comments from Robin Murphy to v1 by moving devices
iommu_fwspec check to gart_iommu_add_device().

Dropped the "Provide single domain and group for all devices" patch from
the series for now because after some more considering it became not
exactly apparent whether that is what we need, that was also suggested
by Robin Murphy in the review comment. Maybe something like a runtime
IOMMU usage for devices would be a better solution, allowing to implement
transparent context switching of virtual IOMMU domains.

Some very minor code cleanups, reworded commit messages.

Dmitry Osipenko (19):
iommu/tegra: gart: Remove pr_fmt and clean up includes
iommu/tegra: gart: Clean up driver probe errors handling
iommu/tegra: gart: Ignore devices without IOMMU phandle in DT
iommu: Introduce iotlb_sync_map callback
iommu/tegra: gart: Optimize mapping / unmapping performance
dt-bindings: memory: tegra: Squash tegra20-gart into tegra20-mc
ARM: dts: tegra20: Update Memory Controller node to the new binding
memory: tegra: Don't invoke Tegra30+ specific memory timing setup on
memory: tegra: Adapt to Tegra20 device-tree binding changes
memory: tegra: Read client ID on GART page fault
iommu/tegra: gart: Integrate with Memory Controller driver
iommu/tegra: gart: Fix spinlock recursion
iommu/tegra: gart: Fix NULL pointer dereference
iommu/tegra: gart: Allow only one active domain at a time
iommu/tegra: gart: Don't use managed resources
iommu/tegra: gart: Prepend error/debug messages with "GART:"
iommu/tegra: gart: Don't detach devices from inactive domains
iommu/tegra: gart: Simplify clients-tracking code
iommu/tegra: gart: Perform code refactoring

.../bindings/iommu/nvidia,tegra20-gart.txt | 14 -
.../memory-controllers/nvidia,tegra20-mc.txt | 23 +-
arch/arm/boot/dts/tegra20.dtsi | 13 +-
drivers/iommu/Kconfig | 1 +
drivers/iommu/iommu.c | 8 +-
drivers/iommu/tegra-gart.c | 466 +++++++-----------
drivers/memory/tegra/mc.c | 83 +++-
drivers/memory/tegra/mc.h | 6 -
include/linux/iommu.h | 1 +
include/soc/tegra/mc.h | 29 +-
10 files changed, 287 insertions(+), 357 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra20-gart.txt


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