Messages in this thread Patch in this message | | | From | Bharat Bhushan <> | Subject | [PATCH] powerpc/e200: Skip tlb1 entries used for kernel mapping | Date | Tue, 24 Jul 2018 11:29:45 +0530 |
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E200 have TLB1 only and it does not have TLB0. So TLB1 are used for mapping kernel and user-space both. TLB miss handler for E200 does not consider skipping TLBs used for kernel mapping. This patch ensures that we skip tlb1 entries used for kernel mapping (tlbcam_index).
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> --- arch/powerpc/kernel/head_fsl_booke.S | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index bf4c602..951fb96 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S @@ -801,12 +801,28 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) /* Round robin TLB1 entries assignment */ mfspr r12, SPRN_MAS0 + /* Get first free tlbcam entry */ + lis r11, tlbcam_index@ha + lwz r11, tlbcam_index@l(r11) + + /* Extract MAS0(NV) */ + andi. r13, r12, 0xfff + cmpw 0, r13, r11 + blt 0, 5f + b 6f +5: + /* When NV is less than first free tlbcam entry, use first free + * tlbcam entry for ESEL and set NV */ + rlwimi r12, r11, 16, 4, 15 + addi r11, r11, 1 + rlwimi r12, r11, 0, 20, 31 + b 7f +6: /* Extract TLB1CFG(NENTRY) */ mfspr r11, SPRN_TLB1CFG andi. r11, r11, 0xfff - /* Extract MAS0(NV) */ - andi. r13, r12, 0xfff + /* Set MAS0(NV) for next TLB miss exception */ addi r13, r13, 1 cmpw 0, r13, r11 addi r12, r12, 1 -- 1.9.3
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